//****** RAM WRAP for B2RAM ******//
// RAM TYPE    :  Sample Dual Port RAM
// Port A      :  Used as write port, 64-bits*64
// Read  Port  :  Used as read port, 64-bits*64, 2-cycles latency for read operation, 

module OH_TSOH_B2RAM_WRAP(
    CLKA,
    WEA,
    ADDRA,
    DINA,
    CLKB,
    ADDRB,
    DOUTB
   );

input                    CLKA;
input                    WEA;
input[5:0]               ADDRA;
input[63:0]              DINA;
input                    CLKB;
input[5:0]               ADDRB;
output[63:0]             DOUTB;



XLNX_V6LX64D_64        INST_RAM(
   .a                  ( ADDRA[5:0] ),
   .d                  ( DINA[63:0] ),
   .clk                ( CLKA ),
   .we                 ( WEA ),
   .qspo               ( ),
   .dpra               ( ADDRB[5:0] ),
   .qdpo_clk           ( CLKB ),
   .qdpo               ( DOUTB[63:0] )
   );

endmodule
